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?1 CXB1575AQ e97y13-ps 155mbps clock & data recovery with high sensitivity limiting amplifier description the CXB1575AQ achieves 3r optical-fiber communi- cation receiver functions (reshaping and regenerating and retiming) on a single chip. this ic also equipped with the signal interruption alarm output, which is used to discriminate the existence of data input. features auto-offset canceler circuit signal interruption alarm output no reference clock required single 3.3v power supply applications sonet/sdh: 155.52mbps atm: 155.52mbps absolute maximum ratings supply voltage v cc ?v ee ?.3 to +5.0 v storage temperature tstg ?5 to +150 ? input voltage difference: | v d ? dn | vdif 0 to 2.5 v ttl input voltage vint ?.5 to 5.5 v output current (continuous) i o 0 to 50 ma (surge) 0 to 100 ma recommended operating conditions supply voltage v cc ?v ee 3.069 to 3.465 v termination voltage (for rck/rdata) v cc ?v t1 1.8 to 2.2 v termination voltage (for sde) v t2 v ee v termination resistance (for rck/rdata) r t1 46 to 56 termination resistance (for sde) r t2 460 to 560 operating temperature ta ?0 to +85 ? sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. 40 pin qfp (plastic)
?2 CXB1575AQ block diagram and pad configuration v ee r2 dn d v cc r down hys v ee r3 cap2 cap3 nc lpfa v ee r1 cap1 cap1b v cc p lpfb v ee p2 nc v ee p1 v ee p1 rext lkdt v ee g v cc g exck cksel sqlch sdc sde sden v cc e2 rck rckn v ee e2 v cc g v ee g v ee e1 rdata rdatan v cc e1 charge pump vco peak hold peak hold phase/ frequency detector reset d ck mux. 1 0 d-ff up down 40 39 38 37 36 34 32 33 21 22 23 24 25 26 27 28 29 30 2 4 5 6 7 8 9 10 1 35 3 16 17 18 19 20 11 12 13 14 15 31
?3 CXB1575AQ pin description pin no. 1 v cc e1 3.3 11 nc no connect 7 v ee e2 0 ground for rck/rckn outputs circuits. 4 v ee e1 0 ground for rdata/rdatan output circuits. 10 v cc e2 3.3 positive supply for rck/rckn output circuits. 5, 33 v ee g 0 ground for digital circuits. 6, 34 v cc g 3.3 positive supply for digital circuits. positive supply for rdata/rdatan output circuits. 2 rdatan 1.6 to 2.4 3 rdata 1.6 to 2.4 retimed data outputs. symbol typical pin voltage (v) dc ac equivalent circuit description v cc e1 v ee e1 2 3 8 rckn 1.6 to 2.4 9 rck 1.6 to 2.4 recovered clock outputs. v cc e2 v ee e2 8 9 12 13 cap3 2 cap2 2 connect a peak hold capacitor for signal detector. typically 470pf. v cc r v ee r 10p 5a 5a 12 13
?4 CXB1575AQ pin no. 14 v ee r3 0 15 hys 0.2 ground for signal detector. connect to v ee r3 through an external resistor to determine signal detect hysteresis width ( ? p). when connect to v ee r3 directly; ? p 6db (typ.) when connected 8.2k to v ee r3; ? p 3db (typ.) symbol typical pin voltage (v) dc ac equivalent circuit description v cc r v ee r3 bias generator 15 16 down 3 17 v cc r 3.3 18 d 19 dn 22 cap1 2.2 23 cap1b 2.2 connect to v cc r through an external resistor to decrease signal detect level (sdl). when open, sdl sets to 18mvp-p. (single-ended) positive supply for signal detector. 20 v ee r2 0 ground for post amplifier. serial data stream inputs. connect an external capacitor, which determines low cut-off frequency for dc feedback loop. typically 0.22?. v cc r v ee r3 16 v cc r v ee r2 v ee r1 18 19 22 23 21 v ee r1 0 24 v cc p 3.3 positive supply for pll circuits. ground for post amplifier. both v ee r1 and v ee r2 must be grounded.
?5 CXB1575AQ pin no. lpfa 3.1 25 26 lpfb 3.1 27 v ee p2 0 connect an external loop filter capacitor. typically 0.68? (155.52mbps). ground for pll circuits. 28 nc no connect 29, 30 v ee p1 0 31 rext 0.4 connect to v ee p1 through an external resistor to determine vco frequency. typically 1.8k . ground for pll circuits. both v ee p1 and v ee p2 must be grounded. symbol typical pin voltage (v) dc ac equivalent circuit description v cc p v ee p1 v ee p2 25 26 v cc p v ee p2 bias generator 31 32 lkdt lock detector (ttl). driven low, while synchronization is lost. 0.2 to 3.1 v cc g v ee g 32 35 exck 1.3 external clock input (ecl). for testing only. normally, left open. v cc g v ee g 35
?6 CXB1575AQ pin no. symbol typical pin voltage (v) dc ac equivalent circuit description 36 cksel 3.3 clock selector (ttl). when low, exck is active instead of vco output. normally, left open. v cc g v ee g 36 37 sqlch 3.3 ttl input. when low, rck and rdata are fixed low, in case of data loss. when high, rck outputs vco free-run frequency, in case of data loss. v cc g v ee g 37 38 sdc 0.2 to 3.1 signal detect output (ttl). driven low, while input serial data is lost. v cc g v ee g 38 39 sde 1.6 to 2.4 40 sden 1.6 to 2.4 signal detect outputs (ecl). sde is driven low, while input serial data is lost. v cc g v ee g 39 40
?7 CXB1575AQ electrical characteristics dc characteristics (v cc = +3.069 to +3.465v, v ee = gnd, ta = ?0? to +85?) item supply current ttl input high voltage ttl input low voltage rdata/rck output high voltage rdata/rck output low voltage sde output high voltage sde output low voltage ttl output high voltage ttl output low voltage maximum input voltage amplitude d/db input resistance i cc v iht v ilt v oh 1 * 1 v ol 1 * 1 v oh 2 * 1 v ol 2 * 1 v oht v olt vmax rin all outputs open 51 to v cc ?2v 51 to v cc ?2v 510 to v ee 510 to v ee i oh = ?.2ma i ol = 2.1ma 2 0 v cc ?1.1 v cc ?1.88 v cc ?1.1 v cc ?1.88 2.4 1600 2250 70 3000 100 3.465 0.8 v cc ?0.83 v cc ?1.55 v cc ?0.83 v cc ?1.55 0.5 3750 ma v v v v v v v v mv symbol min. typ. max. unit conditions * 1 ta = 0? to +85? item post amplifier gain signal detect hysteresis width signal detect response assert time * 1 signal detect response deassert time * 1 jitter generation * 2 pll band width * 2 jitter peaking * 2 jitter tolerance * 2 , * 3 pll capture range * 2 pll pull in time * 2 rck, rdata output rise time rck, rdata output fall time gl ? p tas tdas r j f c tp tr tf hys = v ee r3, rd = 22k with 12khz high pass filter f = 10hz f = 30hz f = 300hz f = 6.5khz f = 65khz drsel = high drsel = high 51 to v cc ?2v, 20% to 80% 51 to v cc ?2v, 20% to 80% 50 3 0 2.3 1.5 1.5 1.5 1.5 0.15 155.40 0.008 90 0.06 16 16 16 4 0.5 155.52 42 600 600 8 100 100 130 0.1 155.60 1000 1000 db db ? ? uirms khz db uip-p mbps ms ps ps symbol min. typ. max. unit conditions ac characteristics (v cc = +3.069 to +3.465v, v ee = gnd, ta = ?0? to +85?) * 1 d = 155.52mbps, pn23-1 pattern, 100mvp-p single-ended, rd = open, cap2/3 = 470pf * 2 d = 155.52mbps, pn23-1 pattern, 20mvp-p single-ended, cp = 0.68? * 3 bit error rate threshold: 1e ?10
?8 CXB1575AQ dc electrical characteristics measurement circuit 1.8k w 510 w 510 w 0.68f 0.22f 470pf 470pf 51 w 51 w 2v 51 w 51 w 2v 3.3v vcc v ee charge pump vco peak hold peak hold phase/ frequency detector reset d ck mux. 1 0 d-ff up down 40 39 38 37 36 34 32 33 21 22 23 24 25 26 27 28 29 30 2 4 5 6 7 8 9 10 1 35 3 16 17 18 19 20 11 12 13 14 15 31
?9 CXB1575AQ ac electrical characteristics measurement circuit z = 50 w 1.8k w 0.68f 0.22f 470pf 470pf ?.3v 0.1f 0.01f 0.01f 33f 0.1f 50 w 50 w z = 50 w z = 50 w z = 50 w z = 50 w clock data pulse pattern generator jitter source oscilloscope clock data bit error rate counter 50 w 50 w 50 w oscilloscope 1m w 1m w 1m w 1m w 510 w 510 w 0.1f +2v 0.1f charge pump vco peak hold peak hold phase/ frequency detector reset d ck mux. 1 0 d-ff up down 40 39 38 37 36 34 32 33 21 22 23 24 25 26 27 28 29 30 2 4 5 6 7 8 9 10 1 35 3 16 17 18 19 20 11 12 13 14 15 31
?10 CXB1575AQ application circuit 1.8k w 0.22f 0.01f 0.1f analog supply2 0.1f digital supply analog supply1 470pf 470pf 0.68f 0.1f 130 w 91 w 91 w 130 w 0.01f 33f 40h digital supply analog supply1 analog supply2 3.3v 33f charge pump vco peak hold peak hold phase/ frequency detector reset d ck mux. 1 0 d-ff up down 40 39 38 37 36 34 32 33 21 22 23 24 25 26 27 28 29 30 2 4 5 6 7 8 9 10 1 35 3 16 17 18 19 20 11 12 13 14 15 31 application circuits shown are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
?11 CXB1575AQ c1 c1 c2 r1 r1 r2 r2 to ic interior d 18 19 22 23 fig. 1 f1 f2 frequency gain feedback frequency response amplifier frequency response fig. 2 notes on operation 1. limiting amplifier block the limiting amplifier block is equipped with the auto-offset canceler circuit. when external capacitors c1 and c2 are connected as shown in fig. 1, the dc bias is set automatically in this block. external capacitor c1 and ic internal resistor r1 determine the low input cut-off frequency f2 as shown in fig. 2. similarly, external capacitor c2 and ic internal resistor r2 determine the high cut-off frequency f1 for dc bias feedback. since peaking characteristics may occur in the low frequency area of the amplifier gain characteristics depending on the f1/f2 combination, set the c1 and c2 so as to avoid the occurrence of peaking characteristics. the target values of r1 and r2 and the typical values of c1 and c2 are as indicated below. when a single-ended input is used, provide ac grounding by connecting pin 19 to a capacitor which has the same capacitance as capacitor c1. r1 (internal): 3k r2 (internal): 10k f2: 5.3khz f1: 7.2khz c1 (external): 0.01? c2 (external): 0.22?
?12 CXB1575AQ rd c r cs rh cs : 470pf c r : 470pf 12 13 14 15 16 17 data input (d) assert time deassert time alarm output (sden) alarm output (sde, sdc) hysteresis width alarm setting level fig. 5. timing chart 2. alarm block this block provides a signal interruption alarm output used for open fibre control (ofc). signal detect threshold level and hysteresis width are both user adjustable. signal detect threshold default level is 18mvp-p (single-ended). an external resister rd between down and v cc r decrease it. typical characteristics of rd vs. threshold level is shown in fig. 7, 8. hysteresis width can be also decreased by an external resister r h . typical characteristics of r h vs. ? p is shown in fig. 9. timing chart of signal detect function is shown in fig. 5. sd response assert/deassert time are decided by peak hold capacitor c r and c s .their typical value is 470pf for 155mbps operation. fig. 3 3db 3db alarm setting input level hysteresis input electrical signal amplitude sd output high level low level small large v das v as v das ? deassert level v as ? assert level fig. 4
?13 CXB1575AQ 3. clock and data recovery block clock recovery is reallized by fully integrated phase locked loop (pll), which needs no external reference clock. pll accepts scrambled nrz data with 50% mark density. two external components re and cp are required. their recommended values are shown in fig. 6. re cp re : 1.8k w cp : 0.68f (155.52mbps) 25 26 27 29 30 31 fig. 6 re is a resistor which decides vco center frequency. to reduce the temperature dependence of the vco oscillation frequency, re should have a small temperature coefficient. in addition, re should place as near as ic terminal to obtain good jitter performance. cp is a loop filter capacitance. since loop damping factor x is function of cp, cp is also important to have a small temperature coefficient. damping factor x is given as 20,000 cp (@ r = 1/2) * 3 recommended cp value gives a x of 10, and jitter peaking of under 0.1db is specified. * 3 r : data transition density 4. others pay attention to handling this ic because its electrostatic discharge strength is weak.
?14 CXB1575AQ 20 15 10 5 0 1 10 100 1000 vast (mvp-p) vdast (mvp-p) fig. 7. rd vs. sd assert/deassert level (rh = 0 w ) v cc = 3.3v, ta = 27? d = 155.52mbps, prbs23-1 20mvp-p, single-ended rh = 0 w rd [k w ] assert/deassert level [mvp-p, single-ended] 20 15 10 5 0 1 10 100 1000 vast (mvp-p) vdast (mvp-p) fig. 8. rd vs. sd assert/deassert level (rh = 8.2k w ) v cc = 3.3v, ta = 27? d = 155.52mbps, prbs23-1 20mvp-p, single-ended rh = 8.2k w rd [k w ] assert/deassert level [mvp-p, single-ended] vast (mvp-p) vdast (mvp-p) 20 15 10 5 0 0 5 20 25 fig. 9. rh vs. sd assert/deassert level (rd = ) v cc = 3.3v, ta = 27? d = 155.52mbps, prbs23-1 20mvp-p, single-ended rd = w rh [k w ] assert/deassert level [mvp-p, single-ended] 10 15
?15 CXB1575AQ ?0 ?5 ?0 ?5 ?0 10 2 10 3 10 6 10 7 fig. 11. jitter transfer function modulation frequency [hz] 10 4 10 5 5 0 ? jitter amplitude [db] oc-3 mask v cc = 3.3v, ta = 27? d = 155.52mbps, prbs23-1 20mvp-p, single-ended 1 0.1 10 2 10 3 10 6 fig. 12. jitter tolerance modulation frequency [hz] 10 4 10 5 100 10 amplitude [ui] v cc = 3.3v, ta = 27? d = 155.52mbps, prbs23-1 20mvp-p, single-ended threshold = 1e ?10 oc-3 template fig. 10. rck/rdata output waveform v cc = 3.3v, ta = 27? d = 155.52mbps, prbs23-1 20mvp-p, single-ended 400mv/div 1.0ns/div example of representative characteristics
?16 CXB1575AQ package outline unit: mm sony code eiaj code jedec code package material lead treatment lead material package mass epoxy resin solder / palladium 42/copper alloy package structure plating 0.2g qfp-40p-l01 qfp040-p-0707 40pin qfp (plastic) 9.0 0.4 + 0.4 0.3 ?0.1 1 10 11 20 21 30 31 40 1.5 ?0.15 + 0.35 0.127 ?0.05 + 0.1 (8.0) a a detail 0.1 ?0.1 + 0.15 + 0.15 7.0 ?0.1 0.5 0.2 0.1 m 0.24 0.65 0?to 10

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